Shift left logical and shift right logil on mips

Shift left logical and shift right logil on mips

can anyone tell if this is the corect code for shift left logical and
shift right logical on mips?
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-- Company:
-- Engineer:
--
-- Create Date: 16:23:58 11/26/2012
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating ---- any
Xilinx primitives in this code. --library UNISIM; --use
UNISIM.VComponents.all;
entity ALU is
Port ( RdData1 : in STD_LOGIC_VECTOR (31 downto 0);
RdData2 : in STD_LOGIC_VECTOR (31 downto 0);
FAddr : in STD_LOGIC_VECTOR (15 downto 0);
ALUSrc : in STD_LOGIC;
ALUOP : in STD_LOGIC_VECTOR (2 downto 0); --S-a marit lungimea lui
ALUOP
Y : out STD_LOGIC_VECTOR (31 downto 0));
end ALU;
architecture Behavioral of ALU is
signal SEAddr : std_logic_vector(31 downto 0);
signal OP2 : std_logic_vector(31 downto 0);
begin
SEAddr(15 downto 0) <= FAddr(15 downto 0);
SEAddr(31 downto 16) <= x"0000" when FAddr(15)='0' else x"FFFF";
OP2 <= RdData2 when ALUSrc ='0' else SEAddr;
with ALUOP select
Y <= RdData1 + OP2 when "000",--S-a marit lungimea lui ALUOP
RdData1 - OP2 when "001",--S-a marit lungimea lui ALUOP
RdData1 AND OP2 when "010",--S-a marit lungimea lui ALUOP
RdData1 OR OP2 when "011",--S-a marit lungimea lui ALUOP
RdData1(30 downto 0) &"0" when "100", --sll ,
"0" & RdData1(1 downto 31) when "101", --srl ,
RdData1 when others;
end Behavioral;